module mux_4X1(
    input i0, i1, i2, i3,  // Four input lines
    input s0, s1,      // Two select lines
    output o1          // Output
);
    wire w1, w2;

    // First stage: Select between A, B and C, D
    mux m1(w1, i0, i1, s0);
    mux m2(w2, i2, i3, s0);

    // Second stage: Select final output
    mux m3(o1, w1, w2, s1);
endmodule

module mux(
    output sel,  // Output of 2x1 MUX
    input a, b,  // Inputs
    input en     // Select line
);
    wire enb, o1, o2;
    
    not n(enb, en);   // Invert the select signal
    and m1(o1, en, a);
    and m2(o2, enb, b);
    or con(sel, o1, o2);  // Final output
endmodule

      ab
      00  01  11  10
cd -------------------
00 |  0    0    0    1  
01 |  1    0    0    0  
11 |  1    0    1    0  
10 |  1    0    1    1  

solving the kmap give the expression 
  f= (ab'd') + (abcd) + (a'b'(c+d))
   a and b are select variables

module top_module (
    input wire a, b, c, d,
    output wire f
);
    wire [3:0] mux_in;
         //solving the kmap give the expression 
        // f= (ab'd') + (abcd) + (a'b'(c+d))
        // a and b are select variables
    
    assign mux_in[0]= c ? 1 : (d ? 1 : 0)  ,   // c OR d
        mux_in[1]= 0,	// zero
       mux_in[2]= d ? 0 : 1,		// not D
     mux_in[3]= c ? (d ? 1 : 0) : 0;      // c AND D
    
 

    // 4-to-1 Multiplexer (Assuming already implemented in Weekly Blog 1)
    mux_4X1 mux_final (mux_in[0], mux_in[1], mux_in[2], mux_in[3],b,a,f);

endmodule

`timescale 1ns / 1ps

module top_module_tb;
    // Declare input signals
    reg a, b, c, d;
    
    // Declare output signal
    wire f;

    // Instantiate the DUT (Device Under Test)
    top_module uut (
        a,b,c,d,f
    );

    // Apply test cases
    initial begin
        $monitor("Time=%0t | a=%b, b=%b, c=%b, d=%b | f=%b", $time, a, b, c, d, f);
        
        // Apply all 16 possible input combinations
        a = 0; b = 0; c = 0; d = 0; #10;
        a = 0; b = 0; c = 0; d = 1; #10;
        a = 0; b = 0; c = 1; d = 0; #10;
        a = 0; b = 0; c = 1; d = 1; #10;
        
        a = 0; b = 1; c = 0; d = 0; #10;
        a = 0; b = 1; c = 0; d = 1; #10;
        a = 0; b = 1; c = 1; d = 0; #10;
        a = 0; b = 1; c = 1; d = 1; #10;
        
        a = 1; b = 0; c = 0; d = 0; #10;
        a = 1; b = 0; c = 0; d = 1; #10;
        a = 1; b = 0; c = 1; d = 0; #10;
        a = 1; b = 0; c = 1; d = 1; #10;
        
        a = 1; b = 1; c = 0; d = 0; #10;
        a = 1; b = 1; c = 0; d = 1; #10;
        a = 1; b = 1; c = 1; d = 0; #10;
        a = 1; b = 1; c = 1; d = 1; #10;

        $finish; // End the simulation
    end
endmodule