Designing a 4×1 Multiplexer Using 2×1 Multiplexers in Verilog

Introduction

A multiplexer (MUX) is a fundamental combinational circuit that selects one out of multiple input signals and forwards it to the output based on the select lines. Multiplexers are widely used in data selection, signal routing, and digital logic design.

In this blog, we will design a 4×1 MUX using 2×1 MUX modules in Verilog, explaining the hierarchy and working principles.

What is a multiplexer?

A multiplexer (MUX) is a combinational circuit with:

• Multiple inputs (data lines).

• Select lines to choose which input gets forwarded to the output.

• One output that carries the selected input value.

A 4×1 MUX has 4 inputs, 2 select lines, and 1 output. The select lines determine which of the four inputs appears at the output.

How to Implement a 4×1 MUX Using 2×1 MUX?

A 2×1 MUX selects one of two inputs based on a single select line (S).
The output equation is:

Y=(S⋅A)+(~S⋅B)Y

To design a 4×1 MUX, we use three 2×1 MUX modules in a hierarchical structure:

1. MUX 1: Selects between i0 and i1 (using S0).

2. MUX 2: Selects between i2 and i3 (using S0).

3. MUX 3: Takes the outputs of MUX 1 and MUX 2 and selects the final output using S1.

   
   

   

   
   

Verilog Code for 4×1 MUX Using 2×1 MUX

Step 1: 2×1 Multiplexer Module:

module mux(
    output sel,  // Output of 2x1 MUX
    input a, b,  // Inputs
    input en     // Select line
);
    wire enb, o1, o2;
    
    not n(enb, en);   // Invert the select signal
    and m1(o1, en, a);
    and m2(o2, enb, b);
    or con(sel, o1, o2);  // Final output
endmodule

Step 2: 4×1 Multiplexer Using 2×1 MUX

module mux_4X1(
    input i0, i1, i2, i3,  // Four input lines
    input s0, s1,      // Two select lines
    output o1          // Output
);
    wire w1, w2;

    // First stage: Select between A, B and C, D
    mux m1(w1, i0, i1, s0);
    mux m2(w2, i2, i3, s0);

    // Second stage: Select final output
    mux m3(o1, w1, w2, s1);
endmodule

Testbench for Verification

To verify our 4×1 MUX, we create a testbench that applies different input values and checks the output.

module mux_4X1_tb();
    reg i0, i1, i2, i3;
    reg s0, s1;
    wire y;

    // Instantiate the 4x1 MUX module
    mux_4X1 uut(i0, i1, i2, i3, s0, s1, y);

    initial begin
        $monitor("Time = %0d | A = %b B = %b C = %b D = %b | S1 = %b S0 = %b | Output Y = %b", 
                 $time, i0, i1, i2, i3, s1, s0, y);
        
        // Test cases
        i0 = 0; i1 = 1; i2 = 1; i3 = 0;
        s1 = 0; s0 = 0; #10; 
        s1 = 0; s0 = 1; #10;
        s1 = 1; s0 = 0; #10; 
        s1 = 1; s0 = 1; #10; 
        
        $finish;
    end
endmodule

Simulation Output

After running the simulation, we expect the following output:

Time = 0  | i0 = 0 i1 = 1 i2 = 1 i3 = 0 | S1 = 0 S0 = 0 | Output Y = 0
Time = 10 | i0 = 0 i1 = 1 i2 = 1 i3 = 0 | S1 = 0 S0 = 1 | Output Y = 1
Time = 20 | i0 = 0 i1 = 1 i2 = 1 i3 = 0 | S1 = 1 S0 = 0 | Output Y = 1
Time = 30 | i0 = 0 i1 = 1 i2 = 1 i3 = 0 | S1 = 1 S0 = 1 | Output Y = 0

Conclusion

• We successfully implemented a 4×1 multiplexer using 2×1 multiplexers.

• The hierarchical approach allows modular design and reusability.

• The testbench verified that the output changes correctly based on select lines.